Staff LLVM Compiler Engineer
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About the Role
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.
Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Location Options: Sunnyvale, Toronto, or Vancouver
About the Role
We are seeking a Compiler Engineer to help design and implement new features in our low-level compiler toolchain including the compiler mid-end, backend, assembler, and linker targeting individual cores in this unique architecture. You’ll work primarily within the LLVM infrastructure, developing code generation and optimization strategies for both existing and future architectures.
This role focuses on generating highly optimized single-core code, foundational to scaling performance across our massively parallel system.
Responsibilities
- Design and implement low-level compiler components (compiler backend, assembler, linker) targeting single cores.
- Automate generation of new LLVM targets using high-level architecture description
- Identify and develop novel LLVM mid-end and backend passes that leverage architectural features and optimize code generation for performance, including memory usage, instruction scheduling, and register allocation.
- Analyze performance bottlenecks and iterate on codegen strategies for complex workloads.
- Work closely with hardware architects, kernel developers, and high-level language designers to ensure end-to-end performance.
- Participate in technical reviews, design discussions, and collaborative debugging.
Requirements
- Bachelor’s, Master’s, PhD, or foreign equivalents in computer science, engineering, or related field
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