Senior IC Design Engineer – IO Signal Integrity & Power Delivery
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About the Role
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.
Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Senior IC Design Engineer – IO Signal Integrity & Power Delivery
About the Role
In this role, you’ll be at the center of high-speed IO interface design and integration, driving the signal integrity (SI) and power delivery (PI) performance of custom IP within our wafer-scale engine.
This position emphasizes complete system analysis, architecture, integration and circuit design from transistor level to external voltage regulator, to ensure that custom and third-party IP meets performance, power, and reliability targets across die, 3d assembly, and system level boundaries.
You’ll collaborate closely with design, packaging, and system engineers to architect and validate custom DDR-like interfaces, IO circuits, and power delivery networks. This is a hands-on technical leadership role for an engineer who understands how circuit behavior, interconnect design, and system integration combine to define product success.
Key Responsibilities
- Own IO signal integrity and power delivery analysis for custom and third-party IP integration in full system stack: die level, 3d integration, board level
- Define interface architecture and design specifications, including signaling schemes, impedance targets, and power distribution requirements.
- Perform and review channel modeling, IBIS-AMI/SPICE simulations, and system-level SI/PI analysis to ensure timing and margin robustness.
- Collaborate with internal and external IP providers to evaluate, select, and integrate custom IO and PHY solutions.
- Lead power delivery network (PDN) modeling and IR-drop analysis, driving improvements across chip, package, and board.
- Support silicon bring-up, validation, and correlation of simulation results to lab measurements.
- Provide technical direction on ESD design, IO reliability, and aging (NBTI, PBTI, HCI).
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