Advanced Packaging Technologist & Lead
About the Role
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.
Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Advanced Packaging Technologist & Lead
We are seeking an accomplished Advanced Packaging Technologist & Lead to drive the development, integration, and deployment of next‑generation semiconductor packaging technologies. This role is critical in architecting and implementing advanced, high‑performance, and high‑density packaging solutions supporting cutting‑edge compute, AI, and heterogeneous integration platforms.
Key Responsibilities
Advanced Packaging Architecture & Development
- Design and implement advanced semiconductor packaging technologies, including 2.5D/3D stacking, heterogeneous integration, high-bandwidth interconnects, and advanced power-delivery architectures.
- Lead R&D in Chip-on-Wafer (CoW) and Wafer-to-Wafer (W2W) bonding approaches for high-density integration.
- Develop and optimize solutions using silicon interposers, Through-Silicon Vias (TSVs), and multi‑layer RDL packaging to enable ultra‑high‑bandwidth and low‑latency connections.
- Engineer advanced packaging structures using low‑CTE substrates, FLEX interconnects, and organic or ceramic substrate technologies.
- Align internal architects and external partners to deliver manufacturable designs and steer our strategic technology direction.
- Leverage simulation-driven de
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