Senior Staff Engineer - AI Workloads & Storage

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are building the next generation of NAND/SSD storage systems designed for the demands of large-scale AI. As the compute cost of transformer inference falls, the bottleneck is shifting to how quickly and efficiently we can move model weights, KV cache, and activations through the storage hierarchy - and NAND flash and SSDs are increasingly the tier where that data lives. Our focus is on making SSDs first-class citizens in the AI data path, from the NAND media and flash-translation layer up through NVMe and networked storage.

We are looking for a Sr Staff Engineer who lives at the intersection of AI inference systems and storage/systems software. This is a hands-on technical leadership role: you will characterize real AI workloads, translate what you learn into architecture, and drive that direction across inference, platform, and hardware teams. This is a rare seat for someone who is equally comfortable reading a transformer serving stack and a Linux block-layer trace.

What You’ll Do

• Own AI workload characterization. Profile production and emerging LLM inference, RAG, and training workloads to quantify their I/O, bandwidth, latency, and capacity demands, and turn those findings into concrete storage and memory-hierarchy design decisions.
• Identify optimal data placement. Analyze workload access patterns to determine how data should be placed and separated on flash, and map those insights onto SSD data-placement technologies such as NVMe Flexible Data Placement (FDP) and streams to reduce write amplification and improve endurance, latency, and QoS.
• Collaborate with key customers to identify differentiating SSD capabilities for AI workloads, and develop proof-of-concept implementations as part of those customer engagements - turning workload insights into demonstrable data-path, tiering, and data-placement wins.
• Lead deep-dive performance analysis spanning the inference runtime, the Linux storage and networking stack, and the underlying hardware, tuning for latency, throughput, cost, and GPU utilization.
• Build and evaluate transactional and system-level models of proposed architectures to de-risk decisions before hardware exists, and validate them against measured behavior.
• Engage with the standards and open ecosystem - SNIA (including Storage.AI), MLCommons/MLPerf, and the open inference stack - to align our work with where the industry is heading and to shape it where we can.
• Set technical direction others build on. Make build-vs-buy and architectural calls, establish benchmarking methodology and best practices, and mentor engineers across the org.
• Partner cross-functionally with product, hardware, and research teams, and with external vendors and partners, to bring architectures from concept to deployment.

What You Bring

• Bachelor's degree 15+ years relevant industry experience or Master's degree 13+ years’ experience or PhD with 10+ years relevant industry experience.
• Extensive experience (typically 10–15+ years) in systems, storage, or ML-systems software, with a track record of architecting systems that materially improved performance, reliability, or cost.
• Demonstrated technical leadership and cross-team influence: setting direction, driving decisions across organizational boundaries, and mentoring senior engineers.
• Working knowledge of modern AI inference, especially transformer architectures - attention, KV cache, batching, and the memory/compute trade-offs of serving large models.
• Deep systems-level understanding of the Linux storage stack (block layer, I/O scheduling, NVMe) and of NAND/SSD internals (flash-translation layer, garbage collection, endurance/write-amplification, latency behavior), plus hands-on performance analysis skill (e.g., perf, ftrace, eBPF, blktrace, fio).
• Fluency in Python plus a systems language (C/C++, Rust, or Go).
• MS or PhD in Computer Science, Electrical/Computer Engineering, or a related field preferred - or equivalent practical experience.

Preferred Qualification 

• Hands-on experience with the modern inference stack: vLLM, SGLang, LMCache, NVIDIA Dynamo, TensorRT-LLM, or Triton.
• Familiarity with GPU-adjacent data movement and memory frameworks: NIXL, DOCA / DOCA MemOps, GPUDirect Storage, RDMA, NVMe-oF, and BlueField / DPU offload.
• Understanding of GPU and TPU architecture (memory hierarchy, interconnects, and how accelerator design shapes I/O and data-movement demands) is highly desired.
• Experience with user-mode storage access frameworks: SPDK, uNVMe, libvfn, or similar.
• SSD firmware experience - flash-translation layer, wear-leveling and garbage-collection algorithms, and data-placement features such as FDP / streams / ZNS - ideally paired with the ability to co-design firmware and host-side placement policy from workload characterization.
• AI-workload characterization and benchmarking experience, and familiarity with SNIA Storage.AI and MLCommons / MLPerf.
• Transactional / discrete-event or system-level modeling experience in frameworks such as SystemC, SimPy, or similar.
• Experience with SSD architecture and interfaces - NVMe (including ZNS, Flexible Data Placement / FDP), open-channel SSDs, computational storage - and with PCIe Gen5, CXL, and large-scale GPU-cluster storage (VAST, WEKA, Lustre, Ceph).

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